Initial import into Git

.cargo/config

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+[target.thumbv7m-none-eabi]
+# uncomment this to make `cargo run` execute programs on QEMU
+# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+runner = "gdb-multiarch -q -x openocd.gdb"
+# runner = "gdb -q -x openocd.gdb"
+
+rustflags = [
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]
+
+[build]
+# Pick ONE of these compilation targets
+# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+# target = "thumbv7m-none-eabi"    # Cortex-M3
+# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)

.gitignore

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+**/*.rs.bk
+.#*
+.gdb_history
+Cargo.lock
+target/

Cargo.toml

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+[package]
+authors = ["Paul van Tilburg <paul@luon.net>"]
+edition = "2018"
+readme = "README.md"
+name = "stm32-demo"
+version = "0.1.0"
+
+[dependencies]
+cortex-m = "0.5.8"
+cortex-m-rt = "0.6.5"
+cortex-m-rtfm = "0.4.2"
+cortex-m-semihosting = "0.3.2"
+panic-abort = "0.3.1"
+panic-halt = "0.2.0"
+panic-semihosting = "0.5.1"
+
+[dependencies.hal]
+package = "stm32f4xx-hal"
+version = "0.3.0"
+features = ["rt", "stm32f407"]
+
+[[bin]]
+name = "stm32-demo"
+test = false
+bench = false
+
+[profile.release]
+codegen-units = 1 # better optimizations
+debug = true # symbols are nice and they don't increase the size on Flash
+lto = true # better optimizations

examples/rtfm.rs

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+//! examples/rtfm.rs
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate panic_semihosting;
+
+use cortex_m_semihosting::hprintln;
+use rtfm::app;
+
+#[app(device = hal::stm32)]
+const APP: () = {
+    #[init]
+    fn init() {
+        static mut X: u32 = 0;
+
+        // Cortex-M peripherals
+        let _core: rtfm::Peripherals = core;
+
+        // Device specific peripherals
+        let _device: hal::stm32::Peripherals = device;
+
+        // Safe access to local `static mut` variable
+        let _x: &'static mut u32 = X;
+
+        hprintln!("init").unwrap();
+    }
+};

memory.x

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+/* Memory layout for the STM32F407 */
+MEMORY
+{
+  /* NOTE 1 K = 1 KiBi = 1024 bytes */
+  /* TODO Adjust these memory regions to match your device memory layout */
+  /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */
+  FLASH : ORIGIN = 0x08000000, LENGTH = 1024K
+  CCM : ORIGIN = 0x10000000, LENGTH = 64K
+  RAM : ORIGIN = 0x20000188, LENGTH = 128k - 0x188
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* You may want to use this variable to locate the call stack and static
+   variables in different memory regions. Below is shown the default value */
+/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
+
+/* You can use this symbol to customize the location of the .text section */
+/* If omitted the .text section will be placed right after the .vector_table
+   section */
+/* This is required only on microcontrollers that store some configuration right
+   after the vector table */
+/* _stext = ORIGIN(FLASH) + 0x400; */
+
+/* Example of putting non-initialized variables into custom RAM locations. */
+/* This assumes you have defined a region RAM2 above, and in the Rust
+   sources added the attribute `#[link_section = ".ram2bss"]` to the data
+   you want to place there. */
+/* Note that the section will not be zero-initialized by the runtime! */
+/* SECTIONS {
+     .ram2bss (NOLOAD) : ALIGN(4) {
+       *(.ram2bss);
+       . = ALIGN(4);
+     } > RAM2
+   } INSERT AFTER .bss;
+*/

openocd.cfg

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+# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
+
+# Depending on the hardware revision you got you'll have to pick ONE of these
+# interfaces. At any time only one interface should be commented out.
+
+# Revision C (newer revision)
+#source [find interface/stlink-v2-1.cfg]
+
+# Revision A and B (older revisions)
+source [find interface/stlink-v2.cfg]
+
+#source [find target/stm32f3x.cfg]
+source [find target/stm32f4x.cfg]
+
+# Use hardware reset, connect under reset
+reset_config srst_only srst_nogate

openocd.gdb

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+target extended-remote :3333
+
+# print demangled symbols
+set print asm-demangle on
+
+# set backtrace limit to not have infinite backtrace loops
+set backtrace limit 32
+
+# detect unhandled exceptions, hard faults and panics
+break DefaultHandler
+break HardFault
+#break rust_begin_unwind
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+#break main
+
+monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.txt uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 must match the core clock frequency
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
+load
+
+# start the process but immediately halt the processor
+#stepi
+continue

src/main.rs

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+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_std]
+#![no_main]
+
+#[cfg(debug_assertions)]
+extern crate panic_semihosting;
+
+#[cfg(not(debug_assertions))]
+extern crate panic_abort;
+
+use cortex_m_rt::entry;
+//use cortex_m_semihosting::hprintln;
+use hal::delay::Delay;
+use hal::prelude::*;
+
+#[entry]
+fn main() -> ! {
+    // Get handles to the hardware.
+    let core = cortex_m::Peripherals::take().unwrap();
+    let device = hal::stm32::Peripherals::take().unwrap();
+
+    // Get a clock for the delay.
+    let rcc = device.RCC.constrain();
+    let clocks = rcc.cfgr.freeze();
+    let mut delay = Delay::new(core.SYST, clocks);
+
+    // Set up the LEDs.
+    let gpiod = device.GPIOD.split();
+    let mut leds = [
+        gpiod.pd12.into_push_pull_output().downgrade(),
+        gpiod.pd13.into_push_pull_output().downgrade(),
+        gpiod.pd14.into_push_pull_output().downgrade(),
+        gpiod.pd15.into_push_pull_output().downgrade(),
+    ];
+    let num_leds = leds.len();
+    assert_eq!(num_leds, 4);
+
+    // Blink the LED...
+    loop {
+        for index in 0..num_leds {
+            leds[index].set_high();
+            leds[(index + 1) % num_leds].set_low();
+            delay.delay_ms(500u16);
+        }
+    }
+}