Initial import into Git
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[target.thumbv7m-none-eabi]
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# uncomment this to make `cargo run` execute programs on QEMU
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# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
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# uncomment ONE of these three option to make `cargo run` start a GDB session
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# which option to pick depends on your system
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# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
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runner = "gdb-multiarch -q -x openocd.gdb"
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# runner = "gdb -q -x openocd.gdb"
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rustflags = [
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# LLD (shipped with the Rust toolchain) is used as the default linker
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"-C", "link-arg=-Tlink.x",
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# if you run into problems with LLD switch to the GNU linker by commenting out
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# this line
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# "-C", "linker=arm-none-eabi-ld",
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# if you need to link to pre-compiled C libraries provided by a C toolchain
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# use GCC as the linker by commenting out both lines above and then
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# uncommenting the three lines below
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# "-C", "linker=arm-none-eabi-gcc",
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# "-C", "link-arg=-Wl,-Tlink.x",
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# "-C", "link-arg=-nostartfiles",
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]
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[build]
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# Pick ONE of these compilation targets
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# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
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# target = "thumbv7m-none-eabi" # Cortex-M3
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# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
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target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
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**/*.rs.bk
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.#*
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.gdb_history
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Cargo.lock
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target/
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[package]
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authors = ["Paul van Tilburg <paul@luon.net>"]
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edition = "2018"
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readme = "README.md"
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name = "stm32-demo"
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version = "0.1.0"
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[dependencies]
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cortex-m = "0.5.8"
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cortex-m-rt = "0.6.5"
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cortex-m-rtfm = "0.4.2"
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cortex-m-semihosting = "0.3.2"
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panic-abort = "0.3.1"
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panic-halt = "0.2.0"
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panic-semihosting = "0.5.1"
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[dependencies.hal]
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package = "stm32f4xx-hal"
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version = "0.3.0"
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features = ["rt", "stm32f407"]
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[[bin]]
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name = "stm32-demo"
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test = false
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bench = false
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[profile.release]
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codegen-units = 1 # better optimizations
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debug = true # symbols are nice and they don't increase the size on Flash
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lto = true # better optimizations
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//! examples/rtfm.rs
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#![deny(unsafe_code)]
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#![deny(warnings)]
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#![no_main]
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#![no_std]
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extern crate panic_semihosting;
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use cortex_m_semihosting::hprintln;
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use rtfm::app;
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#[app(device = hal::stm32)]
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const APP: () = {
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#[init]
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fn init() {
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static mut X: u32 = 0;
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// Cortex-M peripherals
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let _core: rtfm::Peripherals = core;
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// Device specific peripherals
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let _device: hal::stm32::Peripherals = device;
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// Safe access to local `static mut` variable
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let _x: &'static mut u32 = X;
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hprintln!("init").unwrap();
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}
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};
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/* Memory layout for the STM32F407 */
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MEMORY
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{
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/* NOTE 1 K = 1 KiBi = 1024 bytes */
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/* TODO Adjust these memory regions to match your device memory layout */
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/* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */
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FLASH : ORIGIN = 0x08000000, LENGTH = 1024K
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CCM : ORIGIN = 0x10000000, LENGTH = 64K
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RAM : ORIGIN = 0x20000188, LENGTH = 128k - 0x188
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}
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/* This is where the call stack will be allocated. */
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/* The stack is of the full descending type. */
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/* You may want to use this variable to locate the call stack and static
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variables in different memory regions. Below is shown the default value */
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/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
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/* You can use this symbol to customize the location of the .text section */
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/* If omitted the .text section will be placed right after the .vector_table
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section */
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/* This is required only on microcontrollers that store some configuration right
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after the vector table */
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/* _stext = ORIGIN(FLASH) + 0x400; */
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/* Example of putting non-initialized variables into custom RAM locations. */
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/* This assumes you have defined a region RAM2 above, and in the Rust
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sources added the attribute `#[link_section = ".ram2bss"]` to the data
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you want to place there. */
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/* Note that the section will not be zero-initialized by the runtime! */
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/* SECTIONS {
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.ram2bss (NOLOAD) : ALIGN(4) {
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*(.ram2bss);
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. = ALIGN(4);
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} > RAM2
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} INSERT AFTER .bss;
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*/
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# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
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# Depending on the hardware revision you got you'll have to pick ONE of these
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# interfaces. At any time only one interface should be commented out.
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# Revision C (newer revision)
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#source [find interface/stlink-v2-1.cfg]
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# Revision A and B (older revisions)
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source [find interface/stlink-v2.cfg]
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#source [find target/stm32f3x.cfg]
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source [find target/stm32f4x.cfg]
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# Use hardware reset, connect under reset
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reset_config srst_only srst_nogate
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target extended-remote :3333
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# print demangled symbols
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set print asm-demangle on
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# set backtrace limit to not have infinite backtrace loops
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set backtrace limit 32
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# detect unhandled exceptions, hard faults and panics
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break DefaultHandler
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break HardFault
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#break rust_begin_unwind
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# *try* to stop at the user entry point (it might be gone due to inlining)
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#break main
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monitor arm semihosting enable
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# # send captured ITM to the file itm.fifo
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# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
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# # 8000000 must match the core clock frequency
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# monitor tpiu config internal itm.txt uart off 8000000
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# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
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# # 8000000 must match the core clock frequency
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# # 2000000 is the frequency of the SWO pin
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# monitor tpiu config external uart off 8000000 2000000
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# # enable ITM port 0
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# monitor itm port 0 on
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load
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# start the process but immediately halt the processor
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#stepi
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continue
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#![deny(unsafe_code)]
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#![deny(warnings)]
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#![no_std]
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#![no_main]
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#[cfg(debug_assertions)]
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extern crate panic_semihosting;
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#[cfg(not(debug_assertions))]
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extern crate panic_abort;
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use cortex_m_rt::entry;
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//use cortex_m_semihosting::hprintln;
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use hal::delay::Delay;
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use hal::prelude::*;
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#[entry]
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fn main() -> ! {
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// Get handles to the hardware.
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let core = cortex_m::Peripherals::take().unwrap();
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let device = hal::stm32::Peripherals::take().unwrap();
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// Get a clock for the delay.
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let rcc = device.RCC.constrain();
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let clocks = rcc.cfgr.freeze();
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let mut delay = Delay::new(core.SYST, clocks);
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// Set up the LEDs.
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let gpiod = device.GPIOD.split();
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let mut leds = [
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gpiod.pd12.into_push_pull_output().downgrade(),
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gpiod.pd13.into_push_pull_output().downgrade(),
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gpiod.pd14.into_push_pull_output().downgrade(),
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gpiod.pd15.into_push_pull_output().downgrade(),
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];
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let num_leds = leds.len();
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assert_eq!(num_leds, 4);
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// Blink the LED...
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loop {
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for index in 0..num_leds {
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leds[index].set_high();
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leds[(index + 1) % num_leds].set_low();
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delay.delay_ms(500u16);
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}
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}
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}
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